Hugo Le Blevec Thesis defense

This thesis explores the deployment of deep learning models, particularly semantic segmentation, on Field-Programmable Gate Arrays (FPGAs), which offer power-efficient, low-latency solutions for resource-constrained systems like autonomous vehicles and drones. While FPGAs have advantages for these applications, they present challenges due to limited computational and memory resources. This research addresses these challenges by focusing on the joint design of neural networks and dataflow architectures on FPGA. Two encoder-decoder models, ResNet18-UNet and ENet, were implemented, and optimized for real-time inference.
P-ENet an optimized version of ENet thanks to neural network architecture design space exploration, achieves state-of-the-art performance with 70.3% mIoU on the Cityscapes dataset, 226 FPS, and 4.2 ms latency. The study concludes that co-designing neural networks and hardware yields better trade-offs between accuracy and hardware performance than compression techniques alone. Power comparisons show this FPGA design offers 1.15 times better power efficiency than an embedded GPU.