Context and challenges

This technological (r-)evolution goes along with a continued increase in demand for higher throughput, lower power consumption and more scalability for all parts of the system including the baseband signal processing on the Physical Layer (PHY). In terms of throughput for example, requirements that go far beyond the tens of Gb/s targeted in the 5G standardization are foreseen. A major source of complexity and power consumption in baseband signal processing for wireless communication systems is the Forward Error Correction (FEC). An efficient FEC is therefore crucial for reliable communications.

Wireless communication systems,
a driving force for connecting our world

Therefore, revisiting 27-year-old Turbo codes, with nowadays advanced knowledge and techniques, in particular recent advances w.r.t. code and decoding algorithm design as well as decoder hardware architectures, can have the potential to transform this code family to appealing contenders for future standardization. Promising results have been obtained lately for Turbo codes. These include recent advancements made in the context of the B5G European project EPIC (which ended in August 2020) in code and decoding algorithm design as well as in hardware architecture and show that the factors limiting the achievable throughput for Turbo decoders are of different nature (in relation to code design, decoding algorithm and hardware architecture), and they can be overcome only if  investigated and considered jointly to make the leap across the throughput gap.

TurboLEAP aims to go beyond what has been studied in the EPIC project and also incorporate new techniques such as spatial coupling jointly with advances in code- algorithm and hardware architecture design.

urbo-LEAP aims at decoding Turbo codes at Tb/s with current silicon technologies and closing the throughput-gap to LDPC and Polar codes

Objectives

Building on these advancements and on the recently acquired know-how, Turbo-LEAP aims at making substantial contributions towards decoding Turbo codes at Tb/s with current silicon technologies closing the large throughput-gap to LDPC and Polar codes. Moreover, this goal shall be achieved while providing considerable frame size flexibility and while keeping most of the major advantages of Turbo codes like built-in rate flexibility. For this, three main challenges have to be addressed en route to viable high-throughput solutions for B5G applications.

First, further improvements in area and power efficiency are necessary. Best previous Turbo decoder implementations featured in the state-of-the-art based on the Parallel MAP (PMAP) and Fully Parallel MAP (FPMAP) architectures  achieve an area efficiency of less than 3 Gb/s/mm² while their LDPC and Polar counterparts achieve tens of Gb/s/mm².

In addition, enabling the support of frame size flexibility as well as the support of medium (500-1000 bit) to large frame sizes (several thousand bits) are crucial to preserve the large coding gains provided by Turbo codes. Providing solutions to these three challenges is at the heart of the five objectives of the Turbo-LEAP project.

1. Improving the Area Efficiency

The prime objective of TurboLEAP is to close this gap by improving the area efficiency by around two orders of magnitude. While this targeted improvement may seem as too ambitious at a first glance, all tasks of all work packages implicitly target this objective and technical decisions will be made favoring improved area efficiency. The candidate decoder hardware architecture for achieving the targeted improvements in area efficiency and throughput is the fully-pipelined iteration-unrolled turbo decoder architecture (UXMAP).

2. Improving the Power efficiency

Investigations and subsequent improvements/-refinements of the power efficiency of the UXMAP decoder architecture are necessary in order to find solutions competitive with respect to LDPC and Polar deccoders. To quantify objective 2: TurboLEAP aims at a power efficiency of around 1 pJ/decoded bit. 

3. Achieving Tb/s for Medium Frame Sizes while Maintaining Flexibility

For a lot of practical use cases, a certain degree of frame size and code rate flexibility is required. While Turbo codes have the advantage of built-in rate flexibility, achieving frame size flexibility for high-throughput decoder hardware architectures is typically costly. Building on recent results obtained for small frame sizes, TurboLEAP aims at providing solutions to flexibly decode medium frame sizes of several hundred bits at a throughput of around Tb/s.

4. Tb/s for Large Frame Sizes

Turbo codes used in 3G and 4G feature information lengths of up to several thousands of bits per frame and, for the LDPC codes used in 5G NR, up to 8448 bits are used. Larger frame sizes reduce protocol overhead and provide an earlier convergence under iterative decoding (i.e. less iterations). In order to provide viable B5G solutions, TurboLEAP targets Tb/s decoding for frame sizes of more than 1000 bits.

5. Spatial Coupling for Turbo Codes in Practical Applications

Spatial coupling has attracted a lot of scientific interest for LDPC codes and the concept has also been studied for certain types of Turbo codes. However to the best of our knowledge, no standard makes use of spatial coupling yet.
One of the reasons is that there are few publications demonstrating practical hardware implementations for either LDPC or Turbo codes. Therefore, TurboLEAP will aim at demonstrating for the first time a hardware implementation for the decoding of spatially-coupled Turbo codes.

Presentations

An EPIC Leap: Revolutionizing Channel Coding to Support 6G Communications

Abstract: Seminar for 6G World, in which Dr. Stefan Weithoffer participates together with Prof. Erdal Arikan (Polaran) and Dr. Onur Sahin (Inter Digital) and presents an overview on the results obtained in the EPIC project leading up to TurboLEAP. An on-demand recording is available after registration.

TurboLEAP Speaker: Stefan Weithoffer

Link:  6G World/

Video Presentations