Workshop "Design of Energy-Efficient Error-Correction Codes"

Workshop on the Design of Energy-Efficient Error-Correction Codes
Lundi 20.04.2020
Horaires :
De 08:00 à 18:00

Adresse :

Délégation CNRS Paris-Villejuif
27 rue Paul Bert
94200 Ivry-sur-Seine

INFORMATION IMPORTANTE :   ÉVÉNEMENT REPORTÉ

Energy reduction has become a major issue in the design of electronic devices, not only for environemental reasons, but also to augment device capabilities under limited computational ressources. In the area of error correction codes, the main challenge is to reduce the decoder energy consumption while preserving the decoding performance. This problem may be addressed by using tools ranging from information and coding theory (performance analysis, code and decoder design, etc.) to hardware implementation (latency and area optimization, etc.). This workshop aims to present the latest advances on the design of energy-efficient error-correction systems, and to explore the connections between the information theory and hardware implementation issues.

https://effective.sciencesconf.org/

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Recent information

Due to Covid-19, the workshop was postponed to an ulterior date.

 

Description

Energy reduction has become a major issue in the design of electronic devices, not only for environemental reasons, but also to augment device capabilities under limited computational ressources. In the area of error correction codes, the main challenge is to reduce the decoder energy consumption while preserving the decoding performance. This problem may be addressed by using tools ranging from information and coding theory (performance analysis, code and decoder design, etc.) to hardware implementation (latency and area optimization, etc.).

This workshop aims to present the latest advances on the design of energy-efficient error-correction systems, and to explore the connections between the information theory, coding aspects, and hardware implementation issues.

 

Confirmed Speakers

Andreas Burg, EPFL, Low-power design for high-throughput LDPC
Emmanuel Boutillon, Lab-STICC, Non-Binary LDPC decoders with low memory requirements
Franklin Cochachin, Lab-STICC, Sign-Preserving Min-Sum LDPC decoders
Fakhredinne Ghaffari, ETIS, Design of High-Performance and Area-Efficient Decoder for 5G LDPC Codes
Jérémy Nadal, Polytechnique Montréal, Energy modeling of LDPC decoders
Bertrand Le Gal, IMS Bordeaux, Hard-decision LDPC decoders
Stephan Weithoffer, IMT Atlantique, Very high throughput Turbo Decoder architectures

 

How to participate

Registration is free but mandatory, please click here to register
If you want to give a talk at the workshop, please send an email to the organizers and provide a tentative title and abstract.

 

Date and Place

The workshop will be held in fall 2020 or spring 2021. It will be conveniently located at Delegation CNRS, Ivry-Sur-Seine, which is very near Paris and reachable by subway.

Full Adress:
CNRS Paris-Villejuif
27 rue Paul Bert
94200 Ivry-sur-Seine
France

Subway: Line 7, Station Porte d'Ivry or Porte de Choisy
Map
: https://www.openstreetmap.org/?mlat=48.8182&mlon=2.3710#map=15/48.8182/2.3710

 

Organizers

Elsa Dupraz, elsa.dupraz@imt-atlantique.fr, IMT Atlantique, France
François Leduc-Primeau, francois.leduc-primeau@polymtl.ca, Polytechnique Montréal, Canada
Emmanuel Boutillon, Emmanuel.Boutillon@univ-ubs.fr, Université de Bretagne Sud, France

Organisateur(s)

Elsa DUPRAZ

Contact(s) & information(s) pratique(s)

elsa.dupraz@imt-atlantique.fr

02 29 00 13 73

Publié le 13.02.2020
Dim Lun Mar Mer Jeu Ven Sam
 
 
 
 
 
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