Energy reduction has become a major issue in the design of electronic devices, not only for environemental reasons, but also to augment device capabilities under limited computational ressources. In the area of error correction codes, the main challenge is to reduce the decoder energy consumption while preserving the decoding performance. This problem may be addressed by using tools ranging from information and coding theory (performance analysis, code and decoder design, etc.) to hardware implementation (latency and area optimization, etc.). This workshop aims to present the latest advances on the design of energy-efficient error-correction systems, and to explore the connections between the information theory and hardware implementation issues.
Contact(s) & information(s) pratique(s)
02 29 00 13 73