Amer BAGHDADI

Poste

Enseignant-chercheur

Localisation

Brest

Coordonnées :

Tél.

+33 2 29 00 10 37
Biographie

Contact

IMT Atlantique
Lab-STICC UMR CNRS 6285
Technopôle Brest-Iroise — CS 83818
29238 Brest Cedex 3
FRANCE

Office : +33 2 29 00 10 37
Fax : +33 2 29 00 11 84
Email : Amer.Baghdadi@imt-atlantique.fr

Short Biography

Amer Baghdadi is a Professor at IMT Atlantique. He received his Engineering degree in 1998, Master of Science degree in the same year and PhD degree in 2002, all from Grenoble INP (Institut National Polytechnique), France. Furthermore, he received the accreditation to supervise research (HDR) in Sciences and Technologies of Information and Communication in 2012 from the University of Southern Brittany, France.
His general technical area concerns both theoretical and practical aspects, and both algorithm development for digital baseband components and corresponding hardware/software implementations and digital circuit design. His research activities target mainly digital communication applications, in addition to other application domains, and more particularly the design of flexible digital physical layer for future wireless communication standards and terminals. Prof. Baghdadi is IEEE Senior Member. He serves on the technical program committee for several international conferences. He co-authored more than 100 papers on scientific journals and proceedings of international conferences.

Research interests

My general research interests concern both theoretical and practical aspects, and both algorithm development for digital baseband components and corresponding hardware/software implementations and digital circuit design. My research activities target mainly digital communication applications, in addition to other application domains, and more particularly the design of flexible digital physical layer for future wireless communication standards and terminals.

Research projects

Here is a list of my participation to different nationally and internationally collaborative research projects:

Current projects

  • Fantastic 5G (2015-2017): Flexible air interface for scalable service delivery within wireless communication networks of the 5th Generation. H2020-ICT-2014-2.
  • GREENCoMM (2012-2016): Gestion Raisonnée et Efficace en Energie des Nœuds de Communication pour la Maison Multimédia. FUI, 14th Call, Competitiveness Cluster Images&Réseaux.

Former projects

  • METIS (2012-2015): Mobile and wireless communications Enablers for Twenty-twenty (2020) Information Society. Integration Project (IP), FP7-ICT-2011-8.
  • UDEC (2008-2011): Universal channel DECoder. ANR (French National Research Agency) Project. Coordinator of the project.
  • AFANA (2007-2010): Application-Field-aware Adaptive Network on chip Architecture. ANR (French National Research Agency) Project.
  • NEWCOM++ (2008-2011): Network of Excellence in Wireless COMmunications. FP7 EU Network of Excellence.
  • TEROPP (2008-2011): Technologies for terminals in opportunistic radio applications. InterCarnots Project, ANR (French National Research Agency).
  • RADAR ACC (2006-2010): Long-range, high-performance radar for active safety applications in the automotive sector. Competitiveness Cluster iDforCAR.
  • NEWCOM (2004-2006): Network of Excellence in Wireless COMmunications. FP6 EU Network of Excellence.
  • R-Puce (2005-2006): Réseau embarqué sur puce. Internal Project to the Institut Télécom (Actions de recherche sur crédits incitatifs).

Responsibilities and services

Here is a list of my participation to various scientific and administrative responsibilities and services related to my research activities:

  • Animation of the research axe “Architectures” as part of the research team “Interaction Algorithm- Silicon” – CACS department of Lab-STICC.
  • Co-animation for Télécom Bretagne of the Thematic Network “Physics and technologies of the communication and the information” (Réseau Thématique RT1).
  • Member of the CNRS GDR SOC-SiP and the GDR ISIS.
  • Reviewer for the call of research projects from the French research agency (ANR).
  • Reviewer for several PhD evaluation committees (France & Europe).
  • Administrative and scientific responsibilities for the Electronics Department of Telecom Bretagne of nine research projects
  • Coordinator of the UDEC national research project (ANR 2008-2011).
  • Co-editor of a special issue on "Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation" VLSI Design journal, 2012.
  • Member of the program and organization committees of several international conferences:
    • IEEE/ACM Design, Automation, and Test in Europe conference (DATE), since 2008.
    • EUROMICRO Conference on Digital System Design (DSD), since 2008.
    • IEEE Symposium on Rapid System Prototyping (RSP), since 2006.
    • IEEE International Workshop on Mobile and Wireless Communication Systems for 2020 and beyond, 2013.
    • IEEE International Conference on Information & Communication Technologies : from Theory to Applications (ICTTA), 2008.
    • IEEE International conference on Science of Electronics, Technologies of Information and Télécommunications (SETIT), since 2007.
    • IEEE International Symposium on Turbo Codes & iterative information processing (ISTC), 2010.
  • Regular reviewer for many journals and many international conferences.

Teaching

My teaching activity covers several topics in the general domain of information processing and digital design (principles and practices).

I am involved in the teaching of several courses, labs, and student projects in this field: digital baseband processing and associated architectures, signal and image processing architectures, embedded system design, advanced digital design, advanced processor architectures, introduction to system engineering, hardware/software codesign.

Supervising

Here is a list of the supervised or co-supervised PhD students, Postdocs, and Engineers. Furthermore, an average of 2-3 internships (Master and Engineer levels) is proposed each year.

Current PhD Students

  • Jeremy Nadal (2014-2017)
    Flexible and energy-efficient hardware architectures for filter-bank multicarrier (FBMC) waveforms: a key enabler for 5G mobile communications
  • Valentin Mena Morales (2013-2016)
    System-level multi-FPGA reconfigurable prototyping methodology – HPC financial applications
  • Houcine Chougrani (2012-2015) Contract with Orange Labs.
    Design and implementation of digital processing algorithms for UWB radio link in BAN networks

Former PhD Students

  • Mostafa Rizk (2011-2014), then Postdoc at Lab-STICC/UBS
    Cotutelle with Lebanese University.
    No Instruction Set Computing for Digital Communication Applications
  • Carlo Condo (2011-2014), then Research fellow at IIT - Istituto Italiano di Tecnologia
    Cotutelle with Politecnico di Torino.
    VLSI decoding architectures: flexibility, robustness and performance
  • Vianney Lapôtre (2010-2013), then Postdoc at LIRMM
    Cosupervising with Lab-STICC/UBS.
    Toward dynamically reconfigurable high throughput multiprocessor turbo decoder in a multi-mode and multi-standard context
  • Purushotham Murugappa (2009-2012), then Postdoc at Télécom Bretagne.
    Towards optimized flexible multi-ASIP architectures for LDPC/Turbo decoding
  • Salim Haddad (2009-2012), then Postdoc at Télécom Bretagne.
    Iterative receivers: scheduling, convergence, and complexity
  • Rachid Al Khayat (2008-2012), then Associate Professor at Kalamoon University, Damascus, Syria.
    Towards an ASIP optimized architecture for multi-standard turbo decoding
  • Chafic Jaber (2007-2011), then Postdoc at CEA-LIST, Saclay, Gif-sur-Yvette.
    CIFRE contract.
    High-level SoC modeling and performance estimation applied to a multi-core implementation of LTE physical layer
  • Micaela Troglia Gamba (2008-2011), then R&D Engineer at ISMB (Istituto Superiore Mario Boella), Italy.
    Cotutelle with Politecnico di Torino.
    Algorithms and architectures for the detection of MIMO signals
  • Atif Raza Jafri (2007-2011), then Researcher at HEC (Higher Education Commission), Pakistan.
    Multi-ASIP architectures for flexible turbo receiver
  • Hazem Moussa (2005-2009), then R&D Engineer at EVE (Emulation and Verification Engineering), Palaiseau.
    Network-on-Chip architectures for multiprocessor channel decoders
  • Olivier Muller (2004-2007), then Associate Professor at Grenoble INP, TIMA Laboratory.
    Generic multiprocessor architectures for high-throughput turbo decoding

Postdoc

  • Purushotham Murugappa (Feb. 2013 to Jul. 2013)
    Hardware architectures and FPGA demonstrators for future wireless communication receivers (5G).
  • Salim Haddad (Dec. 2012 to Nov. 2013)
    Optimization of iterative receivers and complexity reduction towards original implementations.

R&D Engineers

  • Jeremy Nadal (Nov. 2013 to Oct. 2014)
  • Jean-Noel Bazin (2009 to 2012)
  • Jean Saad (2008 to 2010)

Open positions at the Electronics Department are listed at this link.

Further opportunities (Postdoc, PhD, and Internship) can be very probably initiated in case of particular motivations and skills in the underlined research field.

Do not hesitate to <a href="mailto:amer.baghdadi@imt-atlantique.fr">contact</a> me in this case.

Publications HAL